1. Field
Various embodiments of the invention pertain to memory management in processor architectures, and particularly to a multi-threaded processor that may internally reorder output instruction threads.
2. Background
Multi-threaded processors are designed to improve processing performance by efficiently executing multiple data streams (i.e., threads) at once within a single processor. Multiple registers are typically used to maintain the state of multiple threads of execution at one time. Multi-threaded architectures often provide more efficient utilization of various processor resources, and particularly the execution logic or arithmetic logic unit (ALU) within the processor. By feeding multiple threads to the ALU, clock cycles that would otherwise have been idle due to a stall or other delays in the processing of a particular thread may be utilized to service a different thread.